In the fabrication of integrated circuits, a number of well-established processes involve the application of ion beams to semiconductor wafers in vacuum. These processes include, for example, ion implantation, ion beam milling and reactive ion etching. In each instance, a beam of ions is generated in a source and is directed with varying degrees of acceleration toward a target wafer. Ion implantation has become a standard technique for introducing conductivity-altering impurities into semiconductor wafers. A desired impurity material is ionized in an ion source, the ions are accelerated to form an ion beam of prescribed energy and the ion beam is directed at the surface of the wafer. The energetic ions in the beam penetrate into the bulk of the semiconductor material and are embedded in the crystalline lattice of the semiconductor material to form a region of desired conductivity.
The target mounting site is a critical part of an ion implantation system. The target mounting site is required to firmly clamp a semiconductor wafer in a fixed position for ion implantation and, in most cases, to provide cooling of the wafer. In addition, means must be provided for exchanging wafers after completion of ion implantation. Cooling of wafers is particularly important in commercial semiconductor processing wherein a major objective is to achieve a high throughput in terms of wafers processed per unit time. One way to achieve high throughput is to use a high current ion beam so that the implantation process is completed in a shorter time. However, large amounts of heat are likely to be generated by the high current ion beam. The heat can result in uncontrolled diffusion of impurities beyond prescribed limits in the wafer and in degradation of patterned photoresist layers. It is usually necessary to provide wafer cooling in order to limit the maximum wafer temperature to about 100.degree. C.
A number of techniques for clamping a semiconductor wafer at the target mounting site are known in the art. According to one well-known technique, the wafer is clamped against a platen by a peripheral clamping ring which engages the outer periphery of the front surface of the wafer. The front surface of the wafer is exposed for ion implantation. However, the outer periphery of the wafer cannot be utilized for integrated circuit devices since the clamping ring blocks ion implantation of that portion of the wafer. Another disadvantage is that peripheral clamping does not result in physical contact between the wafer and a conventional flat metal platen over the entire wafer surface area. Since the wafer does not physically contact a large percentage of the platen surface that is intended for thermal transfer, the rate of thermal transfer from the semiconductor wafer is significantly reduced in a vacuum environment. Heat transfer by radiation from the wafer is inadequate, except for low current ion beams. In the case of high current ion beams, physical contact between the wafer and the platen over the area of the wafer is required to ensure sufficient cooling by conductive thermal transfer.
A variety of techniques have been disclosed for ensuring a high rate of thermal transfer with peripheral clamping. A contoured heat sink surface for optimizing conductive heat transfer between a wafer and a heat sink is disclosed in U.S. Pat. No. 4,535,835, issued Aug. 20, 1985 to Holden. The heat sink surface is contoured so as to impose a load that results in a uniform contact pressure distribution and a stress approaching the elastic limit of the wafer for a peripherally-clamped wafer.
Another prior art technique for thermal transfer in vacuum involves the use of a thermally-conductive polymer between a semiconductor wafer and a heat sink. A tacky, inert polymer film for providing thermal contact between a wafer and a heat sink is disclosed in U.S. Pat. No. 4,139,051, issued Feb. 13, 1979 to Jones et al. The polymer film disclosed by Jones et al has a sticky surface which is used to advantage to retain the wafer in position during processing. Such a sticky surface is unacceptable in automated processing wherein the wafer must easily be removed after ion beam treatment. The sticky surface can result in wafer breakage and can easily become contaminated.
An automated wafer clamping mechanism utilizing a pliable, thermally-conductive layer between a semiconductor wafer and a heat sink is disclosed in U.S. Pat. No. 4,282,924 issued Aug. 11, 1981 to Faretra. The wafer is clamped at its periphery to a convexly-curved platen having a layer of thermally-conductive silicone rubber on its surface.
The technique of gas conduction has also been utilized for wafer cooling in vacuum. Gas is introduced into a cavity or microscopic voids behind a semiconductor wafer and effects thermal coupling between the wafer and a heat sink. Gas-assisted, solid-to-solid thermal transfer with a semiconductor wafer is disclosed in U.S. Pat. No. 4,457,359, issued Jul. 3, 1984 to Holden.
All of the known prior art peripheral clamping techniques result in wasted wafer area. In many of these configurations, thermal transfer is inadequate due to poor contact between the semiconductor wafer and the platen surface. Furthermore, the curved platens disclosed in the aforementioned U.S. Pat. Nos. 4,535,835 and 4,282,924 introduce a variation in the angle of incidence of the ion beam on the wafer surface for different locations on the wafer surface. In ion implantation, variations in incidence angle can be a serious problem. The depth of penetration of incident ions is a function of incidence angle because of the well-known channeling effect. Therefore, it is desirable in ion implantation to provide a constant angle of incidence of the ion beam on the wafer surface over the surface area of the semiconductor wafer.
A wafer clamping technique which eliminates the requirement for a peripheral clamping ring and which permits use of a flat platen surface is centrifugal clamping. In centrifugal clamping, the wafer site is rotated about an axis of rotation. The platen surface is oriented at an angle with respect to the axis of rotation so that centrifugal force presses the wafer against the platen surface. A thermal transfer technique which utilizes centrifugal clamping and a flat platen surface having a pliable, thermally-conductive polymer layer for effecting thermal transfer is disclosed in U.S. Pat. No. 4,832,781, issued May 23, 1989 to Mears. The disclosed technique provides highly satisfactory cooling performance. However, the requirement for rotating the wafer site in order to provide centrifugal clamping adds complexity and is not always practical.
Another known technique for clamping semiconductor wafers involves the use of electrostatic forces. A dielectric layer is positioned between a semiconductor wafer and a conductive support plate. A voltage is applied between the semiconductor wafer and the support plate, and the wafer is clamped against the dielectric layer by electrostatic forces. An electrostatic wafer clamp is disclosed by G. A. Wardly in "Electrostatic Wafer Chuck for Electron Beam Microfabrication", Rev. Sci. Instrum., Vol. 44, No. 10, Oct. 1972, pp. 1506-1509 and in U.S. Pat. No. 3,993,509 issued Nov. 23, 1976 to McGinty. Electrostatic wafer clamp arrangements which utilize a thermally-conductive material to remove heat from the wafer are disclosed in U.S. Pat. No. 4,502,094, issued Feb. 26, 1985 to Lewin et al, U.S. Pat. No. 4,665,463, issued May 12, 1987 to Ward et al and U.S. Pat. No. 4,184,188, issued Jan. 15, 1980 to Briglia. The Briglia patent discloses a support plate having layers of thermally-conductive, electrically-insulative RTV silicone. Electrostatic wafer clamps are also disclosed in U.S. Pat. No. 4,480,284, issued Oct. 30, 1984 to Tojo et al, U.S. Pat. No. 4,554,611, issued Nov. 19, 1985 to Lewin, U.S. Pat. No. 4,724,510, issued Feb. 9, 1988 to Wicker et al and U.S. Pat. No. 4,412,133, issued Oct. 25, 1983 to Eckes et al.
U.S. Pat. No. 4,520,421, issued May 28, 1985 to Sakitani et al, discloses a specimen supporting device including a pair of specimen attracting portions each having an electrode on the lower surface of an insulating member. When a voltage is applied between the pair of specimen attracting portions, the specimen is electrostatically attracted to the upper surface. The voltage can be AC or DC. An embodiment having eight arcuate specimen attracting portions with voltages of alternately opposite polarities is disclosed.
U.S. Pat. No. 5,103,367, issued Apr. 7, 1972 to Horowitz et al, discloses an electrostatic chuck for semiconductor wafers having at least three electrodes. Two of the electrodes embedded in a dielectric film are energized by an AC supply to provide sine wave fields of controlled amplitude and phase. The relative phases and amplitudes of the electrode voltages are adjusted to null the voltage induced on the surface of the wafer. In one embodiment, the substrate support surface comprises a thin ceramic layer such as sapphire (Al.sub.2 O.sub.3).
Problems associated with prior art electrostatic wafer clamping arrangements include inadequate clamping force, damage to devices on the wafer by charging currents, difficulty in making electrical contact to the semiconductor wafer, and wafer sticking to the platen after the clamping voltage has been removed. In addition, thermal transfer characteristics have usually been inadequate for high current ion implantation applications, since a significant portion of the platen surface area is devoted to making electrical contact with the semiconductor wafer. See, for example, the aforementioned U.S. Pat. No. 4,502,094.
It is a general object of the present invention to provide improved methods and apparatus for electrostatic clamping of workpieces to a support surface.
It is another object of the present invention to provide improved methods and apparatus for electrostatic semiconductor wafer clamping.
It is another object of the present invention to provide electrostatic clamping apparatus that is highly reliable in clamping semiconductor wafers.
It is a further object of the present invention to provide electrostatic wafer clamping apparatus which provides highly efficient thermal transfer to or from a semiconductor wafer.
It is yet another object of the present invention to provide electrostatic wafer clamping apparatus which includes means for effectively cooling a semiconductor wafer during processing in vacuum so as to permit a relatively high level of incident energy.
It a further object of the present invention to provide electrostatic wafer clamping apparatus which avoids damage to devices on a semiconductor wafer by charging currents.
It is still another object of the present invention to provide electrostatic clamping apparatus having a wafer clamping surface which substantially avoids wafer sticking.
It is still another object of the present invention to provide electrostatic wafer clamping apparatus wherein the wafer is released when the clamping voltage is turned off.
It is a further object of the present invention to provide apparatus for clamping a semiconductor wafer wherein the entire wafer surface is exposed at the same angle for processing.
It is still another object of the present invention to provide electrostatic wafer clamping apparatus which is simple in construction and low in cost.